PhD position - Integrated circuits to enhance the performance of resistive-based memories
CEA Tech

PhD position - Integrated circuits to enhance the performance of resistive-based memories

France 31 Oct 2021

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OPPORTUNITY DETAILS

State University
Area
Host Country
Deadline
31 Oct 2021
Study level
Opportunity type
PhD
Specialities
Eligible Countries
This opportunity is destined for all countries
Eligible Region
All Regions

SL-DRT-21-0859

RESEARCH FIELD

New computing paradigms, circuits and technologies, incl. quantum

ABSTRACT

The Phd objective is to explore fine and dynamic tuning circuit techniques, integrated nearby memory cells, to enhance the performance of RRAM.

LOCATION

Département Composants Silicium (LETI)

Laboratoire de Composants Mémoires

Grenoble

CONTACT PERSON

MOLAS Gabriel

CEA

DRT/DCOS//LCM

CEA/GRENOBLE 17 rue des Martyrs38054 Grenoble CEDEX 9

Phone number: 04 38 78 92 56

Email: gabriel.molas@cea.fr

UNIVERSITY / GRADUATE SCHOOL

Université Grenoble Alpes

Ecole Doctorale de Physique de Grenoble

START DATE

Start date on 01-09-2021

THESIS SUPERVISOR

PILLONNET Gael

CEA

DRT/DACLE//LGECA

Minatec Campus, 38054 Grenoble cedex 9, France

Phone number: 0438780215

Email: gael.pillonnet@cea.fr

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